CSM Project Publications

A BibTeX file containing bibliographic information for all publications listed here is also available.

Globally, this publication list is ordered in reverse chronological order. Within a given year, the ordering is alphabetical (by author name).

The primary sponsor of the DSPCAD Group's work in this research area is the US National Science Foundation.

We are also grateful to the following sponsors, who have supported the research in Maryland DSPCAD Research Group at large: Agilent Technologies; Angeles Design Systems, Inc.; the Austrian Marshall Plan Foundation; CoolCAD Electronics; the Defense Advanced Research Projects Agency; the Department of Homeland Security; the Fulbright Specialists Program of the Council for International Exchange of Scholars; IGI Technologies; Intel; the Laboratory for Physical Sciences; the Laboratory for Telecommunication Sciences; Management Communications and Control, Inc.; the Maryland Industrial Partnerships (MIPS) Program; the National Institutes of Health; National Instruments; the National Institute of Standards and Technology; the National Radio Astronomy Observatory; Northrop Grumman Corp.; the Semiconductor Research Corporation; Techno-Sciences, Inc.; Texas Instruments, Inc.; Trident Systems, Inc.; the University of Maryland Graduate School; the US Air Force Office of Scientific Research under the Dynamic Data Driven Applications Systems (DDDAS) Program; the US Air Force Research Laboratory; the US Army Research Laboratory; the US Army Research Office; and the US National Science Foundation.

DSPCAD Group Website.

[lee2021x7]

K. Lee, Y. Lee, A. Raina, Y. Liu, J. Wu, C. Defrancisci, B. Riggan, and S. S. Bhattacharyya. Software synthesis from dataflow schedule graphs. SN Applied Sciences, 3(2):1-20, January 2021. Article No. 142.

[bhat2020x5]

S. S. Bhattacharyya and M. C. Wolf. Research challenges for heterogeneous CPS design, 2020. arXiv:2005.07841 [cs.SE].

[bhat2020x3]

S. S. Bhattacharyya and M. C. Wolf. Research challenges for heterogeneous cyberphysical system design. IEEE Computer Magazine, 53(7):71-75, July 2020.

[lee2020x7]

Y. Lee, Y. Liu, K. Desnos, L. Barford, and S. S. Bhattacharyya. Passive-active flowgraphs for efficient modeling and design of signal processing systems. Journal of Signal Processing Systems, 92(10):1133-1151, October 2020.

[sapi2020x3]

A. Sapio, S. S. Bhattacharyya, and M. Wolf. Runtime adaptation in wireless sensor nodes using structured learning, 2020. arXiv:2006.08666 [eess.SY].

[sapi2020x5]

A. Sapio, S. S. Bhattacharyya, and M. Wolf. Runtime adaptation in wireless sensor nodes using structured learning. ACM Transactions on Cyber-Physical Systems, 4(4):40:1-40:28, July 2020. Article 40.

[sapi2020x1]

A. Sapio, Shuvra Bhattacharyya, and M. Wolf. Efficient model solving for Markov decision processes. In Proceedings of the IEEE Symposium on Computers and Communications, pages 1-5, Rennes, France, July 2020.

[li2019x8]

L. Li, P. Deaville, A. Sapio, L. Anttila, M. Valkama, M. Wolf, and S. S. Bhattacharyya. MADS: A framework for design and implementation of adaptive digital predistortion systems. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 9(4):712-722, December 2019.

[li2019x1]

L. Li, P. Deaville, A. Sapio, L. Anttila, M. E. Valkama, M. Wolf, and S. Bhattacharyya. A framework for design and implementation of adaptive digital predistortion systems. In Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, pages 112-116, Hsinchu, Taiwan, March 2019.

[li2019x3]

L. Li, C. Sau, T. Fanni, J. Li, T. Viitanen, F. Christophe, F. Palumbo, L. Raffo, H. Huttunen, J. Takala, and S. S. Bhattacharyya. An integrated hardware/software design methodology for signal processing systems. Journal of Systems Architecture, 93:1-19, 2019.

[liu2019x2]

Y. Liu, L. Barford, and S. S. Bhattacharyya. Optimized implementation of digital signal processing applications with gapless data acquisition. EURASIP Journal on Advances in Signal Processing, 2019(19):1-13, March 2019.

[sapi2019x3]

A. Sapio. Runtime adaptation in embedded computing systems using Markov decision processes. PhD thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, 2019.

[sapi2019x1]

A. Sapio, R. Tatiefo, S. Bhattacharyya, and M. Wolf. GEMBench: A platform for collaborative development of GPU accelerated embedded Markov decision systems. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, pages 294-308, Samos, Greece, July 2019.

[li2018x4]

L. Li. Design Space Exploration for Signal Processing Systems using Lightweight Dataflow Graphs. PhD thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, 2018.

[lin2018x2]

S. Lin, J. Wu, and S. S. Bhattacharyya. Memory-constrained vectorization and scheduling of dataflow graphs for hybrid CPU-GPU platforms. ACM Transactions on Embedded Computing Systems, 17(2):50:1-50:25, January 2018.

[liu2018x5]

Y. Liu. Model-Based Design and Implementation of Deep Waveform Analysis Systems. PhD thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, 2018.

[liu2018x2]

Y. Liu, L. Barford, and S. S. Bhattacharyya. Generalized graph connections for dataflow modeling of DSP applications. In Proceedings of the IEEE Workshop on Signal Processing Systems, pages 275-280, Cape Town, South Africa, October 2018.

[pelc2018x1]

M. Pelcat, A. Mercat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot, J.-F. Nezan, W. Hamidouche, D. Menard, and S. S. Bhattacharyya. Reproducible evaluation of system efficiency with a model of architecture: From theory to practice. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(10):2050-2063, October 2018.

[sapi2018x2]

A. Sapio, S. S. Bhattacharyya, and M. Wolf. Efficient solving of Markov decision processes on GPUs using parallelized sparse matrices. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing, pages 13-18, Porto, Portugal, October 2018.

[sapi2018x4]

A. Sapio, L. Li, J. Wu, M. Wolf, and S. S. Bhattacharyya. Reconfigurable digital channelizer design using factored Markov decision processes. Journal of Signal Processing Systems, 90(10):1329-1343, 2018.

[ha2017x1]

S. Ha, J. Teich, C. Haubelt, M. Glaß, T. Mitra, R. Dömer, P. Eles, A. Shrivastava, A. Gerstlauer, and S. S. Bhattacharyya. Introduction to hardware/software codesign. In S. Ha and J. Teich, editors, Handbook of Hardware/Software Codesign, pages 1-24. Springer, 2017.

[li2017x2]

L. Li, A. Ghazi, J. Boutellier, L. Anttila, M. Valkama, and S. S. Bhattacharyya. Evolutionary multiobjective optimization for adaptive dataflow-based digital predistortion architectures. EAI Endorsed Transactions on Cognitive Communications, 3(10):1-9, February 2017.

[li2017x3]

L. Li, A. Sapio, J. Wu, Y. Liu, K. Lee, M. Wolf, and S. S. Bhattacharyya. Design and implementation of adaptive signal processing systems using Markov decision processes. In Proceedings of the International Conference on Application Specific Systems, Architectures, and Processors, pages 170-175, Seattle, Washington, July 2017. (PDF)

[pelc2017x1]

M. Pelcat, A. Mercat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot, J.-F. Nezan, W. Hamidouche, D. Menard, and S. Bhattacharyya. Models of architecture: Application to ESL model-based energy consumption estimation. Technical report, IETR/INSA Rennes; Scuola Superiore Sant'Anna, Pisa; Institut Pascal; University of Maryland, College Park; Tampere University of Technology, Tampere, February 2017.

[wolf2017x1]

M. Wolf and S. Bhattacharyya. Stochastic models for optimization of software-defined radio operation. In Proceedings of the Wireless Innovation Forum Conference on Wireless Communication Technologies, pages 28-29, San Diego, California, November 2017.

[bhat2016x1]

S. S. Bhattacharyya and M. Wolf. Tools and methodologies for system-level design. In L. Lavagno, I. L. Markov, G. E. Martin, and L. K. Scheffer, editors, Electronic Design Automation for Integrated Circuits Handbook --- Volume 1: EDA for IC System Design, Verification, and Testing, pages 39-58. CRC Press, Taylor & Francis Group, second edition, 2016.

[li2016x3]

L. Li, A. Ghazi, J. Boutellier, L. Anttila, M. Valkama, and S. S. Bhattacharyya. Design space exploration and constrained multiobjective optimization for digital predistortion systems. In Proceedings of the International Conference on Application Specific Systems, Architectures, and Processors, pages 182-185, London, England, July 2016.

[li2016x1]

L. Li, A. Ghazi, J. Boutellier, L. Anttila, M. Valkama, and S. S. Bhattacharyya. Evolutionary multiobjective optimization for digital predistortion architectures. In Proceedings of the International Conference on Cognitive Radio Oriented Wireless Networks, pages 498-510, Grenoble, France, May 2016.

[pelc2016x1]

M. Pelcat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot, J.-F. Nezan, and S. S. Bhattacharyya. Models of architecture: Reproducible efficiency evaluation for signal processing systems. In Proceedings of the IEEE Workshop on Signal Processing Systems, pages 121-126, Dallas, Texas, October 2016.

[sapi2016x1]

A. Sapio, M. Wolf, and S. S. Bhattacharyya. Compact modeling and management of reconfiguration in digital channelizer implementation. In Proceedings of the IEEE Global Conference on Signal and Information Processing, pages 595-599, Washington, D.C., December 2016.

[wolf2016x1]

M. Wolf, S. S. Bhattacharyya, J. Florence, and A. E. Sapio. Power and thermal modeling for communication systems. In Proceedings of the IEEE Workshop on Signal Processing Systems, pages 136-141, Dallas, Texas, October 2016.

[pelc2015x1]

M. Pelcat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot, J.-F. Nezan, and S. S. Bhattacharyya. Models of architecture. Technical Report PREESM/2015-12TR01, IETR/INSA Rennes, 2015. HAL Id: hal-01244470. (PDF)