`timescale 1ns / 1ps `define state_idle 3'b000 `define state_read_address 3'b001 `define state_write_data_A 3'b010 //`define state_write_data_B 3'b110 //`define state_read_data_B 3'b011 `define state_write_data 3'b011 `define state_send 3'b100 `define state_send_A 3'b101 `define state_send_B 3'b110 `define state_send_C 3'b111 ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 23:14:33 10/23/2014 // Design Name: // Module Name: MEM_block // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module MEM_block( inout [1:0] DQbus, inout DQS, input clk, input reset, input CE, input CLE, input ALE, input WE//, //output reg [7:0] address_buffer, //output reg [2:0] cur_state, //output reg [9:0] data_counter ); reg [7:0] address_buffer; reg [2:0] cur_state; reg [9:0] data_counter; reg [2:0] next_state; wire [1:0] Data_out [0:15]; wire [1:0] Data_w; reg [1:0] Data_buf; assign Data_w = ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b0000 == address_buffer[6:3]))? Data_out[0] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b0001 == address_buffer[6:3]))? Data_out[1] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b0010 == address_buffer[6:3]))? Data_out[2] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b0011 == address_buffer[6:3]))? Data_out[3] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b0100 == address_buffer[6:3]))? Data_out[4] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b0101 == address_buffer[6:3]))? Data_out[5] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b0110 == address_buffer[6:3]))? Data_out[6] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b0111 == address_buffer[6:3]))? Data_out[7] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b1000 == address_buffer[6:3]))? Data_out[8] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b1001 == address_buffer[6:3]))? Data_out[9] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b1010 == address_buffer[6:3]))? Data_out[10] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b1011 == address_buffer[6:3]))? Data_out[11] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b1100 == address_buffer[6:3]))? Data_out[12] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b1101 == address_buffer[6:3]))? Data_out[13] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b1110 == address_buffer[6:3]))? Data_out[14] : ((cur_state == `state_send || cur_state == `state_send_B)&& (4'b1111 == address_buffer[6:3]))? Data_out[15] : 2'b00; always @ (posedge clk) begin if((cur_state == `state_send || cur_state == `state_send_B )) Data_buf <= Data_w; else Data_buf <= 2'bZZ; end assign DQbus = (cur_state == `state_send || cur_state == `state_send_B || cur_state == `state_send_C) ? Data_buf :2'bZ; assign DQS = ((cur_state == `state_send || cur_state == `state_send_B || cur_state == `state_send_C) ) ? ~clk : 1'bZ; wire MEM_WE; assign MEM_WE = (cur_state == `state_write_data) ? ~DQS : 1'b0; wire [12:0] ADDR = {address_buffer[2:0], data_counter}; always @ (negedge clk) begin if(cur_state == `state_read_address && ALE ==1) address_buffer <= {DQbus,address_buffer[7:2]}; else if(cur_state == `state_idle) address_buffer <= 8'b0; else address_buffer <= address_buffer; if(cur_state == `state_send || cur_state == `state_write_data || cur_state == `state_send_A ) begin data_counter <= data_counter+10'b1; end else begin data_counter <= 10'b0; end end always @(*) begin case (cur_state) `state_idle: begin if((CLE == 1 && WE ==0 && DQbus == 2'b01) || (CLE == 1 && WE ==0 && DQbus == 2'b00)) next_state = `state_read_address; else next_state=`state_idle; end `state_read_address: begin if(ALE == 1 && WE == 0 && CLE ==0) next_state = `state_read_address; else if(ALE ==0 && CLE == 1 && WE == 0 && DQbus == 2'b10) next_state = `state_send_A; else if(ALE == 0 && WE == 1 && CLE ==0) next_state = `state_write_data_A; else next_state = `state_idle; end `state_write_data_A: next_state = `state_write_data; //`state_write_data_B: // next_state = `state_write_data; `state_write_data: begin if(data_counter == 10'b1111111111) next_state = `state_idle; else next_state = `state_write_data; end `state_send_A: begin next_state = `state_send; end `state_send: begin if(data_counter == 10'b1111111111) next_state = `state_send_B; else next_state = `state_send; end `state_send_B: begin next_state = `state_send_C; end `state_send_C: begin next_state = `state_idle; end default: begin next_state = `state_idle; end endcase end always @ (negedge clk or posedge reset) begin if(reset == 1'b1) begin cur_state <= `state_idle; end else begin cur_state <= next_state; end end RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_0( .DO(Data_out[0]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b0000 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_1( .DO(Data_out[1]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b0001 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_2( .DO(Data_out[2]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b0010 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_3( .DO(Data_out[3]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b0011 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_4( .DO(Data_out[4]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b0100 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_5( .DO(Data_out[5]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b0101 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_6( .DO(Data_out[6]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b0110 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_7( .DO(Data_out[7]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b0111 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_8( .DO(Data_out[8]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b1000 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_9( .DO(Data_out[9]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b1001 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_10( .DO(Data_out[10]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b1010 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_11( .DO(Data_out[11]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b1011 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_12( .DO(Data_out[12]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b1100 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_13( .DO(Data_out[13]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b1101 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_14( .DO(Data_out[14]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b1110 == address_buffer[6:3])) ); RAMB16_S2 #( .INIT(2'b00), .SRVAL(2'b11), .WRITE_MODE("WRITE_FIRST") ) mem_block_15( .DO(Data_out[15]), .ADDR(ADDR), .CLK(~clk), .DI(DQbus), .EN(1'b1), .SSR(1'b0), .WE(MEM_WE & (4'b1111 == address_buffer[6:3])) ); endmodule