Course Information:
Lecture: | Mon 1:00 - 1:50, EGR-1202 |
Mailing List: | enee245-01all-fall16@coursemail.umd.edu |
Recommended Text: | Smith & Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice Hall |
Instructor Information:
Professor: | Bruce L. Jacob, Electrical & Computer Engineering |
Office: | 1333 A.V. Williams Building |
Phone: | (301) 405-0432 |
Email: | |
Office Hours: | Open-door policy ... |
Teaching Assistants: |
Sec. | Name | Office Hours | |
0101 | Candace Walden | cbwalden@umd.edu | Monday 5-7pm |
0103 | Candace Walden | cbwalden@umd.edu | Monday 5-7pm |
0102 | Soumya Indela | indela.soumya@gmail.com | Thursday 6-7pm, Friday 10-11am |
0122 | Soumya Indela | indela.soumya@gmail.com | Thursday 6-7pm, Friday 10-11am |
0104 | Drew Risinger | drisingr@umd.edu | Wednesday 5-7pm |
0107 | Drew Risinger | drisingr@umd.edu | Wednesday 5-7pm |
0105 | Rajdeep Talapatra | rajdeep.joy@gmail.com | Friday 5-7pm |
0106 | Rajdeep Talapatra | rajdeep.joy@gmail.com | Friday 5-7pm |
0108 | Sheung (Shawn) Lu | sheunglu@umd.edu | Friday 9-10am |
0110 | Matt Jennings | jennings@umd.edu | Tuesday 5-6pm |
0111 | Y. Dwith Chenna | cyndwith@umd.edu | Thursday 5-6pm |
Course Handouts and General Information:
Data Sheets and Equipment Manuals:
Regarding Pre-Lab Reports:
We have strict guidelines that the TAs are not to allow students into the lab who do not come with a well-prepared pre-lab writeup. So please make sure that you have detailed pre-lab reports with all the details about Design and Simulation carefully presented. If you have any question regarding the pre-lab, make sure you reach out to your TA before your lab, and get it clarified. Here are a few guidelines that will help you with pre-lab and post-lab preparation:Pre-Labs:
Post-Labs:
Please contact your TA if you have any questions.
Labs:
Lab # | Week of | Topic | Documenation |
0 | Aug 29 | Tutorials on lab equipment & software | PSpice Tutorial.docx
Xilinx Tutorial 1.doc Xilinx Tutorial 2.doc |
1 | Sep 5 | Combinational logic (adders) | Lab1.pdf |
2 | Sep 12 | Sequential logic (clocks, registers) | Lab2.pdf
DLA Tutorial.docx |
3 | Sep 19 | Simple state machine: saturating counter | Lab3.pdf
DLA.docx datasheets for all the components |
4 | Sep 26 | Intro to MOSFETs and voltage boosting | Lab4.pdf
Lab4-2N7000.pdf |
5 | Oct 3 | Verilog fundamentals | Lab5.pdf
Nexys2_500General.ucf |
6 | Oct 10 | Verilog and FPGA advantages | Lab6.pdf |
7 | Oct 17 | Multiplexers -- two types, and Verilog synthesis | Lab7.pdf |
8 | Oct 24 | Seven-Segment Displays | Lab8.pdf |
9 | Oct 31 | Finite State Machines: Vending-Machine Controller | Lab9.pdf
debouncer.v |
10 | Nov 7 | Memories and Control -- Some Basics | Lab10.pdf
debouncer.v MEM_block.v |
11 | Nov 14 | Memories and I/O -- Bidirectional Data | Lab11.pdf
debouncer.v MEM_block.v |
12 | Nov 21 | LCD Calculator | Lab12.pdf
keyboard_final.zip PmodCLP_rm_RevA.pdf |
Training Videos for the Lab Equipment: