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Doing Layout With Cadence

Bringing Cells Together: Hierarchical Design

Hierarchical design is an extremely important concept in layout design. If, for instance, I were to lay out a chip like this one by placing every transistor at the transistor level on the chip scale, when the time came to tape out this design for fabrication the end-result file would be impossibly huge.
But that chip, and practically every chip, actually includes many units repeated many times, smaller than the full chip design but larger than single transistors. Logic gates are such units. One level up, structures like latches are made up of repeating gates. One level up, structures like counters are made up of repeating latches.
Layout design programs are designed to exploit this repetitiveness by allowing the designer to include the whole of a "lower level" cell in a "higher level" cell, so that for instance once you've designed a NAND gate and need a flip-flop, you do not need to lay out four individual transistors to use as a NAND gate in the flip-flop design; you can simply "call" your NAND gate and insert it in your flip-flop cell.
The example on this page is very simplistic in that it brings just two gates together to make one slightly larger gate, but the mechanics of joining smaller cells together to make a larger one remains the same all the way up to the chip level.

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On to Part 8: Bonding pad frame and chip creation .
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Zeynep Dilli
Last modified: Fri Oct 24 13:51:19 EDT 2003