ECE Ph.D. Student Ayooluwa (“Ayo”) Ajiboye Recognized at APEC 2024

ECE Ph.D. student Ayooluwa (“Ayo”) Ajiboye, was awarded two Best Presentation Awards at the IEEE Applied Power Electronics Conference (APEC) held recently in Long Beach, California. He is advised by Professor Alireza Khaligh. The two awarded papers are a result of an ongoing NSF-funded research work on the design of a 54kW electrothermally integrated traction inverter underway in the Maryland Power Electronics Laboratory (MPEL).

The first paper recognized is titled “Modelling the Effect of the DC Link Decoupling Capacitor of a Commutation Power Loop Using a Thevenin-Based Frequency Domain Approach”. In this work, Ayooluwa discusses wide band-gap devices and how their high commutation speed can cause voltage overshoots and oscillatory behavior across the drain-source port. He proposes a Thevenin-based frequency domain approach for modelling the switch voltage overshoot and oscillations present in the commutation power loop. The accuracy of the proposed model is validated experimentally and takes into account the slew rates associated with practical MOSFET devices. In this paper, he obtains recommendations which are useful in the design and implementation of DC-DC and DC-AC converters. These recommendations are related to the sizing of the decoupling capacitors and the optimum placement of these capacitors which are both very useful in the design, PCB layout and hardware implementation.

The second paper that was awarded is titled “Modeling the Effect of Gate-Drain Parasitic Capacitance of a SiC MOSFET in a Half-Bridge During the Soft Turn-Off and Hard Turn-On Transition”. In this work, a novel frequency-domain approach to quantify the effect of the gate-drain parasitic capacitance of a SiC MOSFET is proposed. This paper addresses the oscillatory issues that arise in the gate loops of wide bandgap MOSFETs due to their high commutation speeds. The oscillations that occur across the drain-source port of the device can be coupled to the gate-source port through the miller gate-drain parasitic capacitance. The propagation of these oscillations to the gate loop can cause a mis-triggering of the soft turned-off device during the hard turn-on transition of the complementary switch in a half-bridge structure. The presented analytical model allows for the optimal design and PCB layout of the gate drive circuitry of a power MOSFET as it considers its associated parasitic elements. The model also takes into account the active miller clamp feature that is integrated in the newer generation of gate drivers.

Ayooluwa is a Nigerian member of the Maryland Power Electronics Lab (MPEL). His research interests include: High-frequency bi-directional DC-AC converters, SiC bare-die based traction inverters, Solar microinverters, Grid-connected inverters, Battery Management Systems, and the Characterization of wide-bandgap power switches.

After receiving these two awards, Ayooluwa says “I am thankful to Professor Khaligh for providing me with this great opportunity and for his constant support and guidance as I progress through the Ph.D. program.” In addition, he thanks his co-authors on both papers, Ayodhya Gamwari Somiruwan, and Dr. Rakesh Resalayyan for their integral contributions to both research outcomes. Ayodhya is a fellow ECE Ph.D. student and member of MPEL. Dr. Rakesh recently completed his postdoctoral study in the ECE department and was a member of MPEL.

The IEEE APEC conference recently concluded and as such, both papers will be made publicly available in the near future on the IEEE database. Once publicly available, both papers will be found here: https://ieeexplore-ieee-org.proxy-um.researchport.umd.edu/author/37297731800

Published March 21, 2024