Event
Ph.D. Research Proposal Exam: Jacob Alan Young
Friday, September 11, 2026
10:00 a.m.
AVW 2460
Souad Nejjar
301 405 8135
snejjar@umd.edu
ANNOUNCEMENT: Ph.D. Research Proposal Exam
Name: Jacob Young
Committee:
Professor Rajeev Barua (Chair)
Professor Saikat Guha
Professor Sennur Ulukus
Date/time: Friday, September 11 at 10:00 AM
Location: AVW 2460
Title: Hierarchical Compilation for Utility-Scale Fault-Tolerant Quantum Computing
Abstract: Fault-tolerant quantum computing (FTQC) has the potential to solve intractable problems in cryptography and materials science but requires executing algorithms containing millions or billions of operations. The fundamental bottleneck is physical runtime. A naively compiled circuit could take years to run, rendering advanced hardware functionally useless, whereas a structurally optimized implementation compresses that execution to days or weeks. Without aggressive, physically tractable circuit compression, these world-changing applications will remain permanently out of reach.
The compilation choice space is astronomically large. High-level algorithmic choices have complex interactions with the underlying quantum computing hardware, and emerging FTQC architectures rely on complex logical instruction set architectures (ISAs) where certain operations are nearly free while others require immense overhead. Most existing compilers reduce algorithms to flattened gate-level netlists, destroying algorithmic structural context, blinding the compiler to high-level algorithmic swaps and the means to exploit the underlying ISA and restricting compiler optimizations to localized gate-rewrites. Conversely, emerging high-level frameworks preserve structure but often act merely as abstract resource estimators, failing to perform rigorous, cost-aware lowering to real ISAs.
This proposal argues that hierarchical circuit synthesis enables end-to-end compilation of utility-scale quantum algorithms into executable programs for emergent FTQC ISAs. It observes that FTQC compilation strongly resembles hierarchical digital hardware design, and optimizations that are intractable at the gate level may become trivial given higher-level structural context. The proposed framework replaces flat pipelines with a hierarchical synthesis tree, handling macroscopic choices early and delaying fine-grained time-dependent scheduling. This approach allows the compiler to solve the right problem at the right abstraction level. Unlike abstract resource estimators, this framework explicitly lowers semantic structures to heavily constrained logical ISAs, providing exact resource and cost accounting while enabling targeted technology mapping that flattened compilers cannot perform.
The methods described in this proposal are not hypothetical—they have been built, evaluated, tested, and applied to a variety of applications, both identifying application bottlenecks for real fault-tolerant ISAs and directly informing codesign of those ISAs, demonstrating a strong feedback loop and the viability of the overall approach. Future work consists of leveraging the proposed framework for more applications, developing new techniques and optimizations, and continuing to demonstrate the codesign and compilation capabilities needed to bring world-altering quantum applications to fruition.
