Event
Ph.D. Research Proposal Exam: Abir Ahsan Akib
Tuesday, October 20, 2026
12:00 p.m.
AVW 2224
Souad Nejjar
301 405 8135
snejjar@umd.edu
ANNOUNCEMENT: Ph.D. Research Proposal Exam
Name: Abir Ahsan Akib
Committee:
Professor Ankur Srivastava (Chair)
Professor Dana Dachman-Soled
Professor Manoj Franklin
Date/time: Tuesday, October 20, 2026 at 12:00 PM
Location: AVW 2224
Title: Hardware Security in Advanced Packages: Metrics and Vulnerabilities
Abstract: Advanced packaging and heterogeneous integration are increasingly used to improve the performance, scalability, yield, and design flexibility of modern computing systems. By integrating multiple chiplets and technologies within a common package, these architectures enable greater modularity and reuse, but they also introduce hardware security concerns that are not fully captured by assumptions developed for monolithic systems. These concerns arise both during hardware development, where adversaries may possess prior knowledge of protected designs, and after deployment, where physically separated chiplets continue to interact through shared package-level resources. This research investigates these challenges through security metrics and vulnerability analysis, with emphasis on quantifying information exposure and characterizing timing-based leakage in advanced packages.
The first part of this work examines how adversarial knowledge affects the security of logic-locked hardware. We introduce the Knowledge-Guided Oracle-Less Attack (KOLA), which models an experienced manufacturing-stage adversary possessing a locked netlist and a library of previously encountered designs. KOLA exploits functional information exposed by the key-independent portions of a locked circuit and uses a matching metric to quantify the similarity between the protected design and designs in the adversary's knowledge library. This provides a means to characterize information leakage from logic-locking techniques and evaluate how adversarial experience influences their effectiveness.
The work then investigates timing-based vulnerabilities in heterogeneously integrated processors, where physically separated chiplets continue to communicate through shared Network-in-Package resources. We demonstrate that contention within these resources creates observable timing variations that can be exploited to infer proprietary interconnect characteristics and sensitive workload behavior. We further show that these timing variations can be intentionally manipulated to establish cross-chiplet covert channels, and evaluate how topology, routing, chiplet placement, encoding strategy, and background traffic affect channel effectiveness. Collectively, this work develops metrics and attack methodologies for characterizing hardware information leakage and motivates security mechanisms specifically designed for advanced packaged systems.
