Ph.D. Dissertation Defense: Meenatchi Jagasivamani

Thursday, January 23, 2020
1:00 p.m.
AVW 2328
Maria Hoo
301 405 3681

ANNOUNCEMENT: Ph.D. Dissertation Defense  
Name: Meenatchi Jagasivamani

Committee Members:
Professor Bruce Jacob, Chair/Advisor 
Professor Robert Newcomb
Professor Martin Peckerar
Professor Donald Yeung
Professor Lourdes Salamanca-Riba, Dean's Representative
Date: Thursday, January 23, 2020 at 1:00 PM to 3:00 PM  
Location:  AVW 2328
Title: Resistive RAM Based Main-Memory Systems:  Understanding the Opportunities, Limitations, and Tradeoffs

As DRAM faces scaling issues as a high-density memory, emerging technologies are being explored as alternatives. One promising candidate is Resistive Memories (ReRAM), which is scalable, vertically stackable, and because of the possibility of integration with standard logic process, can deliver higher density as a main-memory solution. The key differentiator with this approach involves a ReRAM memory array that integrates directly with a logic processor underneath.

In this research work, we explore ReRAM as a main-memory alternative at three levels of detail – at the device level, the physical-design level, and finally at the architecture level. We begin with an overview of ReRAM and compare with alternate technologies. We look at the physical design of the solution and present the results of area studies on integrating a VSCALE processor at the 45nm technology node with a ReRAM bit-cell array. The area study was performed based on parameters specified by our collaborators at Crossbar Inc. The results showed that the optimum operating point is at 50% array efficiency with a VSCALE processor, and that this configuration incurs an area penalty of 18%. 
Two of the key challenges for ReRAM with respect to DRAM performance include the higher write latency requirement (typically on the order of 1us) and the lower write endurance (typically less than 10^8 cycles). This compares with DRAM write-latency times of less than 30ns (depending on technology node and generation) and write endurance of more than 10^15 write cycles. In this research work, we explore the possibility of utilizing the ReRAM cell in an intermediate state between non-volatile state and threshold state, where we intentionally tradeoff the write energy for a much lower data retention. This allows the chip to more easily replace existing DRAM-like main memory applications, without requiring higher write programming current or accommodating for a longer write latency.  We performed this evaluation both at the device-level and at the architecture level.
At the device-level, we used UMD’s Nano-fab lab to construct a Metal-Oxide based ReRAM bitcells on which we characterized the relationship between data-retention and write current applied. Our fabricated ReRAM was composed of Titanium-Oxide and Aluminum Oxide. We also confirmed the behavior of a mixed volatility state where a formed filament relaxes over time to move to a high resistance level. Based on our experimental measurements, operating in the mixed volatile state would reduce write energy by 10 to 100x, and thereby improve the write endurance.

Finally, at the architecture-level, we used the Structural Simulation Toolkit (SST) to characterize a ReRAM-based main-memory system and compare with a DRAM-based one using our research group’s DRAMSIM3 tool. We also characterized the sensitivity of various architectural parameters (core-to-memory controller ratio, queue depth, NoC topology) on system performance on stream and gups-based graph benchmarks which indicated that the torus topology will provide reasonable performance. Impact of the number of parallel processors indicated that at low processor counts, DRAM outperforms ReRAM due to its faster memory latency. However, at high processor counts, ReRAM with its higher number of parallel connections is able to deliver higher system performance than DRAM.

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