Event
Ph.D. Research Proposal Exam: Ubaid Bakhtiar
Tuesday, August 26, 2025
10:00 a.m.
Souad Nejjar
301 405 8135
snejjar@umd.edu
ANNOUNCEMENT: Ph.D. Research Proposal Exam
Name: Ubaid Bakhtiar
Committee:
Professor Bahar Asgari (Chair)
Professor Donald Yeung
Professor Cunxi Yu
Professor Bahar Asgari (Chair)
Professor Donald Yeung
Professor Cunxi Yu
Date/Time: Tuesday, August 26, 2025 at 10:00 AM
Title: Architecting Efficiency – Data Scheduling, Dynamic Reconfiguration, and Multi-Tenancy for Sparse Acceleration
Abstract: As data volumes continue to grow exponentially across domains from scientific computing and graph analytics to machine learning, computation has become increasingly dependent on the exploitation of sparsity. Sparsity, referring to the prevalence of zeros in data, has evolved into a deliberate design goal, playing a critical role in minimizing data movement, reducing memory footprint, and accelerating computation. However, the existence of sparsity also presents a significant architectural challenge: poor resource utilization, which leads to wasted silicon area and limited system scalability. The issue is exacerbated even more in the twilight of Moore's law when the emphasis shifts from simply adding more transistors to extracting more performance from existing hardware. General-purpose processors and specialized accelerators often fail to achieve the theoretical gains offered by sparsity due to underutilized hardware resources. To close the gap between peak and achievable performance, techniques such as data scheduling, multi-tenancy, and dynamic reconfiguration must be integrated into sparse applications hardware to mitigate the high resource underutilization and consequently, fully exploit the benefits of sparsity. Despite advancements in computer architecture and accelerators, applications involving sparse matrix algebra still fail to fully utilize available hardware, primarily due to underutilization. To bring such applications closer to the peak theoretical performance that a given hardware budget can offer, it is necessary to rethink traditional techniques, such as data scheduling and multi-tenancy, and to adopt novel computing paradigms, such as dynamic reconfiguration.
This dissertation addresses the challenges caused by sparsity by demonstrating that data scheduling, dynamic reconfiguration, and multi-tenancy are complementary techniques that significantly improve resource utilization in sparse applications, each targeting distinct inefficiencies and collectively laying the foundation for future unified accelerator architectures. First, this work proposes low-cost, novel data scheduling and placement strategies, such as cross High Bandwidth Memory (HBM) channels data migration, dynamic matrix partitioning, and sparsity pattern prediction, to improve load balance and reduce data movement. Second, this work enables dynamic reconfiguration based on runtime profiling of the structural characteristics of the underlying sparse workloads and the quality of intermediate outputs. Third, this work introduces fine-grained multi-tenancy approaches that enable multiple sparse workloads to share a single hardware platform, maximizing resource utilization while maintaining execution efficiency across tenants. This dissertation also presents hardware architectures that leverage the proposed strategies to accelerate sparse workloads such as scientific solvers, graph analytics and pruned machine learning models by improving resource utilization. It also provides a thorough quantitative analysis of the proposed designs by comparing them against state-of-the-art hardware solutions.
These advancements pave the way for our future work that primarily focuses on building a unified end-to-end accelerator for sparse applications that supports efficient data scheduling, dynamic reconfiguration and multi-tenancy achieving maximum performance given certain resources. The hardware solutions presented in this dissertation lay the foundation for improving resource utilization as a sustainable alternative to relying on continued transistor scaling in the post-Moore’s Law era.
