Event
Ph.D. Research Proposal: Charana Sharada Suenth Sonnadara
Monday, October 27, 2025
10:00 a.m.
AVW 2460
Emily Irwin
301 405 0680
eirwin@umd.edu
ANNOUNCEMENT: Ph.D. Research Proposal Exam
Name: Charana Sharada Suenth Sonnadara
Committee:
Professor Sahil S Shah
Professor Timothy Horiuchi
Professor Xin Zan
Date/time: 27th October, 10:00 am
Location: AVW 2460
Title: ON-CHIP LEARNING WITH NON-VOLATILE FLOATING GATES: A MIXED-SIGNAL PROCESSOR FOR NEURAL INFERENCE
Abstract: Brain-Computer interface (BCI) provides a direct communication path between the brain and external devices, enabling patients with neurological disorders or limb loss to regain communication and motor control in daily tasks. BCIs for motor prosthetic estimate the patient’s intention from intracortical, electrocorticography (ECoG), or electroencephalography (EEG) and decode the patient’s intention to guide the patient’s limb or prosthetic. Further neural signals are nonstationary; therefore, BCI systems must contend with the natural post-implant drift from the electrode-tissue interface changes and physiological factors, which alter signal statistics over time. Consequently, these systems require on-chip adaptations and continuous learning to ensure sustained performance. However, most existing systems rely on power-demanding, tethered bench-top or bulky wearable devices, which constrain real-world use. These limitations motivate the development of implantable, small-form-factor architectures with substantially lower power consumption. These limitations motivate digitally supervised, mixed-signal architectures with non-volatile floating-gate memory to enable accurate, low-power on-device decoding in implantable form factors. The research focuses on developing mixed-signal models that incorporate floating gate (FG) transistors and analog non-volatile Compute-In-Memory (CIM), with on-chip learning and adaptation capabilities. CIM will be used primarily in this processing system to reduce the bottlenecks associated with data movements and utilize the computational capabilities of FG devices. Further, this research aims to address continuous learning and reduce mismatches inherent in analog memory cells, while maintaining flexibility and scalability to support multiple channels and more general analog signal processing demands. The proposed solutions will be focused on, 1. On-Chip implementation of mixed signal processor with neural decoding capabilities: that is capable of operating with ultra-low power, which can perform accurate real-time decoding of kinematics from neural signals, intracortical signals. 2. Developing on-chip learning algorithms: A hardware plausible learning algorithm that (i) estimate facilitates contentious learning, and (ii) applies targeted floating-gate weight updates in CIM arrays to cancel device variation and preserve accuracy. Contributions of this study include an improved, cascaded tile-based floating-gate programming method. Its robustness mechanisms are achieved through the co-design of peripheral circuits, including sampling networks, operational-transimpedance amplifiers, and bias/reference distribution. In addition, the work provides a quantitative analysis of per-device programming on the tile-level transfer characteristics. This work also introduces inter-tile communication with microcontroller-based SoC integration to coordinate weight updates and enable on-chip learning.
