Event

ANNOUNCEMENT: Ph.D. Research Proposal Exam

Name: Mark-yves Gaunin

Committee:

Professor Mohammad Hafezi (Chair)

Professor Agis Iliadis

Professor Cheng Gong

Date/time: Friday, May 15, 2026, 1:00 - 3:00 pm

Location: AVW 1146

Title: The Fundamental Limit of Fabrication in Silicon: Scaling and Characterization of Atomic Quantum Devices

Abstract: 

Silicon chips have dominated modern computing devices, enabling everything from self-driving vehicles to large language models. As the complexity and scale of computing has increased over time, nanofabrication techniques have been developed to make transistors down to the few nanometers scale. Scanning tunneling microscope (STM) enabled hydrogen de-passivation lithography (HDpL) on silicon provides a natural solid-state platform for reaching the fundamental limit of fabrication: manipulation of individual atoms. In this sub-nanometer regime quantum effects become essential, enabling controllable, functional atomic quantum devices.

Patterning a device within a single atomic layer can be achieved by applying voltage pulses from an STM tip onto a hydrogen terminated silicon substrate in ultra-high vacuum (UHV). A precursor dopant gas, such as phosphine, can be introduced into the UHV environment. These precursor molecules will bond to exposed silicon where hydrogen was removed. Degenerately doped regions become conducting, acting as nearly metallic device leads, defined with nanometer- and even single-atom- precision in the lateral dimensions. These leads can be coupled to atomic-scale quantum device elements allowing control of tunnel rates, electron readout times, or enabling local RF reflectometry measurements. Growing epitaxial silicon over the device layer keeps the device shelf-stable outside of an ultra-high vacuum (UHV) environment, potentially for years.

Devices such as single or few donor qubits with single electron transistor (SET) charge sensors and analog quantum simulators (AQS) have been fabricated and measured in our laboratories. Donor/SET devices provide an intuitive platform for realizing an electron or nuclear spin-based quantum computer.  Atom-based analog quantum simulators can be used to study the extended Fermi-Hubbard quantum field theory model. However, there are several key challenges on the immediate horizon that need to be addressed to make more meaningful, reproducible and scalable devices, such as: automation of the lithography process, charge noise reduction, increasing achievable electrical gate ranges, and coherent qubit manipulation. 

Currently, fabricating atomically precise devices in silicon requires expert operators of STMs. Manually intensive tasks and operator-dependent architecture often lead to one-off working devices and low fabrication throughput. Automation of HDpL is a necessary requirement for making STM-dependent fabrication techniques more accessible, reproducible, and scalable. We have developed an open-source automation platform to automatically fabricate STM-patterned leads, including automated STM tip quality detection, tip conditioning, lithography detection, lithography quality, and tip creep correction algorithms. Such automated fabrication routines can be extended to single atom precision through open-source deep learning atomic classification algorithms.

Another key problem has been that atomic devices have limited electrical gate ranges and are highly susceptible to charge noise. A broader gate range will lead to several critical improvements to our devices. It will enable our AQS arrays to mimic a wider variety of materials and complex, many-body physical phenomena. It will also allow for individual and selective loading and unloading of electrons. Donor sites could be fully unloaded reliably, enabling control of the electron number at each site. This would facilitate control of spin pairing and the transition between singlet and triplet states. It would also enable voltage-control of the hyperfine coupling between electrons and surrounding nuclear spins, which could lead to the ability to perform dynamic nuclear polarization (DNP) and to selectively manipulate nuclear spin qubits.

We have demonstrated that encapsulating the quantum device interface with intrinsic silicon increases the achievable gate range of our devices. This encapsulation can be extended from purely intrinsic silicon to isotopically pure Si-28, which has been demonstrated to improve coherence times of qubits in silicon. However, silicide contacts to the buried interface layer must also be optimized to stay within this intrinsic or Si-28 envelope. Silicide formation depth has been studied through various thin film depositions annealed quickly at lower temperatures. However, substantial process optimizations and systematic studies are still required to achieve the level of control and yield needed for reliable device fabrication. Optimized electrical contacts are expected to reduce charge noise with wide and stable gate operation ranges ultimately leading to a higher signal-to-noise ratio for spin readout.

Finally, driving Rabi oscillations for spin-qubit control involves generating well-defined, high frequency control pulses to address individual donor-bound spins. Designing and characterizing electron spin resonance (ESR) lines in the 40 GHz regime is an essential component in achieving reliable pulsing of spin-based qubits. ESR lines designed with large ground planes are found to be less lossy, and thus more thermally efficient. This limits the design area of electrical contacts on the surface of the chip. Therefore, isolating ESR lines on a conformally coated dielectric thin film would reduce design constraints as well as expand layout flexibility for adding top gates for better electron modulation. Studying atomic layer deposition (ALD) dielectric thin films on donor-based quantum chips, and their frequency pulsing characterization will provide the tools for fabricating high-performance ESR lines enabling robust coherent control of qubits.

This proposal aims to make significant advances in three key areas: (1) Automating HDpL will lead to an accessible, reproducible, and scalable platform for fabricating atomic devices. (2) Encapsulating our devices in intrinsic silicon and optimizing silicide contacts to the buried device interface will lead to improved electrical gate ranges and reduced charge noise. (3) Engineering a 3-D stack to fabricate top-gates and ESR lines will enable coherent qubit control. These major challenges must be addressed in order to facilitate electron and nuclear spin manipulation in silicon-based atomic quantum devices, and more exotic applications such as arrays of atoms for applications in lattice gauge theory simulations.