ENEE359F: Intermediate Topics in Computer Engineering; Advanced FPGA System Design using Verilog

Credits: 3

Semesters Offered

Fall 2017, Spring 2018, Spring 2019, Spring 2020
Testudo

Additional Course Information

Course Description

This is a project-oriented course. Based on the knowledge and training gained in ENEE245, students will further develop their skills by working on more challenging digital system design using Verilog hardware description language (HDL) in an industry-standard design environment. Students will implement real-world designs in field programmable gate arrays (FPGAs) as well as test and optimize the FPGA-implemented systems. Students will also work in teams on multiple, medium-scale digital system design projects and make oral presentations and written reports.

Pre-requisites:

Completion of ENEE245 with a "C-" or better.

Course Objectives:

  1. Experience  with advanced  digital system design
  2. Advanced  HDL-based design
  3. Use  of associated CAD tools
  4. FPGA implementation and  testing
  5. Project work and  experimentation
    1. Design,  coding, simulation, and synthesis
    2. Implementation and debugging on  FPGAs
    3. Experiment design
    4. Project  report and oral presentation
  6. Teamwork experience
  1. Communication  skill development
    1. Oral presentations
    2. Written reports

Topics Covered: 

  1. Digital design flow with  FPGAs
  2. Versatility and applications  of FPGAs
  3. Synthesizable  Verilog coding
  4. Advanced digital system  design
  5. Fast computer arithmetic  processing
  6. Pipelining
  7. Floating-point processing
  8. First-In First-Out (FIFO) buffer  design
  9. Error detection and correction  codes
  10. Serial and parallel data  transfer
  11. Host  computer-to-FPGA  and FPGA-to-FPGA communication
  12. Design verification and  debugging
  13. Timing/area/power  analysis  and optimization