ENEE408D: Capstone Design Project: Mixed Signal VLSI Design

Credits: 3

Semesters Offered

Spring 2018, Spring 2019, Spring 2020, Spring 2021, Spring 2022, Spring 2023, Spring 2024
Testudo

Learning Objectives

  • Consolidate and apply key concepts in semiconductor devices, analog circuits and digital circuits introduced earlier in the electrical and computer engineering curricula
  • Select appropriate design problems, partition and distribute design tasks within each team
  • Analyze, design, and optimize complex CMOS integrated circuits including: DC, transient and small signal responses; phase margin, gain, and frequency response trade-offs of op-amps; optimal fan-out and minimum propagation delay of digital circuits
  • Use Computer-Aided Design (CAD) tools such as circuit simulators to confirm analysis and predict performance, layout tools to implement circuit designs on a silicon chip, and verification tools to ensure that the design satisfies design rules and implements the desired circuit;and
  • Understand how semiconductor physics influences chip design rules and sets limits on integrated circuit performance.

Topics Covered

  • CMOS IC design and fabrication
  • CAD tools including schematic capture, circuit simulator, layout editor, DRC, LVS
  • Designing and laying out the integrated circuit well
  • Metal layers, pads, and interconnects
  • Design and layout of active and polysilicon layers
  • MOSFET design, fabrication, and operation
  • Parasitic elements due to layout and device structure, and the resulting RC delay and inductive cross talk
  • Digital CMOS circuits: the operation and layout of the inverter, nand, and, nor gates
  • Advanced circuit simulation
  • Analog CMOS circuits: the operation and layout of current sources, differential amplifiers, active loads, cascode loads, operational amplifiers, frequency compensation, operational transconductance amplifiers
  • Mixed-signal circuits for specific applications (e.g., communications)
  • Design optimization: minimum propagation delay, optimal fan-out
  • Economic motivation for IC circuit fabrication
  • Environmental issues in chip fabrication; use and disposal of dangerous chemicals