Hardware design of digital computers. Arithmetic and logic units, adders, multipliers and dividers. Floating-point arithmetic units. Bus and register structures. Control units, both hardwired and microprogrammed. Index registers, stacks, and other addressing schemes. Interrupts, DMA and interfacing.
Prerequisite: ENEE350; and completion of all lower-division technical courses in the EE curriculum.
Restriction: Permission of ENGR-Electrical & Computer Engineering department.
Credit only granted for: ENEE446 or CMSC411.
Semesters OfferedFall 2017, Spring 2018, Fall 2018, Spring 2019, Fall 2019, Spring 2020, Fall 2020, Spring 2021, Fall 2021, Spring 2022, Fall 2022, Spring 2023
- Introduction to quantitative principles of digital computer design
- Understanding the architecture of current digital computers
- Contemporary issues in computer architecture
- A developmental understanding of computer architecture
- Current and potential roles for parallelism in computer architecture
- Principles of computer design
- Cost/performance of design options
- Processor design
- Instruction set design and implementation
- Pipelining and instruction-level parallelism
- Floating-point arithmetic
- Memory-hierarchy design: caches, main memory, virtual memory
- Input/output design and performance measures, types of I/O devises, connections of I/O to CPU and main memory
- The increasing role of parallelism from fine-grained to coarse-grained; what forms of parallelisms appear to be easier for programmers