Credits: 1
Verilog or VDHL hardware description languages (HDLs) and graphical printed ciruit design CAD packages are used to create a digital system implemented on a printed circuit-board. A practical design for hardware incorporating a processor and interface devices is to be created by the student. Simulation is used to explore practical issues of system performance and device resource constraints, and a printed-circuit board proof-of-concept will be produced by the student.
Description
Minimum grade of C- in ENEE245.Verilog or VDHL hardware description languages (HDLs) and graphical printed ciruit design CAD packages are used to create a digital system implemented on a printed circuit-board. A practical design for hardware incorporating a processor and interface devices is to be created by the student. Simulation is used to explore practical issues of system performance and device resource constraints, and a printed-circuit board proof-of-concept will be produced by the student.
Semesters Offered
Fall 2017, Fall 2018, Fall 2019, Fall 2020, Fall 2021, Fall 2022, Fall 2023, Fall 2024, Fall 2025
TestudoLearning Objectives
- Transform the functional specification for a logic design into a logic description language
- Design a simulation for functional test of the logic design
- Compile the logic design into a physical device using a logic design environment
- Perform a timing analysis of the physical logic device using the logic design environment
- Embed the logic design in a physical system simulation and evaluate performance
Topics Covered
- Schematic design with Webpack
- Designing with verilog HDL
- Verilog simulation
- Mixed schematic/verilog design in Webpack
- Designing with VHDL
- Fitting logic designs to real chips
- System design exercise
- System design simulation and analysis