Credits: 3

Description

Prerequisite: ENEE303 and ENEE350; or students who have taken courses with comparable content may contact the department; or permission of instructor.
Review of MOS transistors: fabrication, layout, characterization; CMOS circuit and logic design: circuit and logic simulation, fully complementary CMOS logic, pseudo-nMOS logic, dynamic CMOS logic, pass-transistor logic, clocking strategies; sub system design: ALUs, multipliers, memories, PLAs; architecture design: datapath, floorplanning, iterative cellular arrays, systolic arrays; VLSI algorithms; chip design and test: full custom design of chips, possible chip fabrication by MOSIS and subsequent chip testing.

Semesters Offered

Spring 2018, Spring 2019, Spring 2020