Ph.D. Dissertation Defense: Timothy Dunlap

Tuesday, April 2, 2024
10:00 a.m.
AVW 1146
Maria Hoo
301 405 3681

ANNOUNCEMENT:  Ph.D. Dissertation Defense 

Name: Timothy Dunlap

Dr. Gang Qu, Chair/Advisor
Dr. Manoj Franklin
Dr. Timothy Horiuchi
Dr. Cunxi Yu
Dr. Alan Sussman, Dean's Representative

Date/Time: Tuesday, April 2, 2024 at 10AM

Location: AVW 1146

Title:  Polymorphic Circuits: The identification of Possible Sources and Applications

Polymorphic gates are gates whose function depends on some external or environmental condition. These external conditions can include temperature, voltage, clock frequency, or an external signal. While there has been research into both the creation and applications of polymorphic gates, much remains unknown. This dissertation explores possible explanations for how evolutionary algorithms create polymorphic gates, subthreshold generation of polymorphic gates, a polymorphic interoperability framework, and two unusual types of polymorphism: time-based and multi-polymorphism. The contributions of this research include multiple aspects of polymorphism. The exploration of the quality of gates created by evolutionary algorithms, a methodology of controlling for the errors generated with evolutionary algorithms, and possible structures that can be used to design polymorphic gates are given in chapter 4. The interoperability of polymorphic gates is given in chapter 3. The evolutionary algorithm is seeded with one structure discovered and the speed and robustness of the resulting gates are tested when polymorphism is tested in the subthreshold domain in 6. Time-based polymorphism is also introduced in chapter 5.

The fundamentals of polymorphic circuits and their applications have been discussed in the existing literature[1,2] and are more extensively detailed in Chapter 2. Each gate has a set function and cannot be used outside the function for which it was created, locking the functionality in place. The framework introduced in Chapter 3 proposes a way to take already existing polymorphic gates and convert them into a polymorphic source that can be used to alter the functionality. This source is a circuit that takes no input other than the external conditions triggering the polymorphism, outputting a signal that switches when the polymorphic conditions change. Some possible applications of this framework are also discussed.

Polymorphic circuits are commonly created with evolutionary algorithms [3]. Because the evolutionary algorithm operates in ways that are not always obvious, precise mechanisms of polymorphism are not immediately clear in the resulting gates. Chapter 4 identifies multiple structures that impact the polymorphic nature of the gates: input sources, loops, threshold drop transistors, and transistors that act as capacitors. When subthreshold polymorphism is examined, input sources are included in the evolutionary algorithm as a seed, and the results show an increase in the quality of polymorphic gates produced. The quality of polymorphic gates is also examined, and a categorization methodology is introduced. This categorization operates on circuits identified by the evolutionary algorithm as candidate circuits. It conducts a series of tests to determine if the gate is an actual polymorphic gate and not just a gate tuned to pass the fitness function in the evolutionary algorithm.

Time-based polymorphism and multi-polymorphism are introduced in Chapter 5. Time-based polymorphism was discovered during the time analysis of evolved polymorphic circuits in chapter 4. This occurs when the function of the circuit depends on the sample rate of the circuit and is based on some input combinations not quickly reaching the output they move towards. For these circuits, care must be taken to have the circuit in a known state before switching the functionality by increasing the sample rate.

In many published polymorphic gates, the gate only exhibits two functions [2,4]. However, this is not a requirement, and some gates can exhibit more than two, with a maximum of 3 researched in this dissertation [1]. Multi-polymorphism is defined as when a circuit has multiple points on the circuit's function map. This map represents all external polymorphic parameters and the functions expressed by the circuits. For a multi-polymorphic circuit, there can be three different functions all related to the same external condition, multiple different external conditions, or two functions related to a single condition, but where the functions change twice along the map.

Chapter 6 introduces polymorphic gates to the subthreshold domain. In this chapter, high-voltage and low-voltage subthreshold polymorphism are considered. High-voltage subthreshold polymorphism means polymorphism that has one level below the threshold and one level that is much higher (VDD = 3.3V in this case). Low-voltage subthreshold is used to describe a voltage below the threshold and one that is just above the threshold. Low-voltage polymorphic gates were evolved using three target voltages: 0.4V, 0.7V, and 1.0V.

High-voltage subthreshold polymorphism was evolved, and the candidate circuits identified were categorized. The runs that had candidate circuits passing categorization were analyzed for power consumption. This power consumption was then compared against a CMOS NAND gate, and the results showed that the evolved gates were less efficient. Possible explanations for this were given along with potential fixes in Chapter 7.

Low-voltage subthreshold polymorphism was evolved in a slightly different way to all other forms of polymorphism presented in this dissertation. Two batches were created, with a slightly different evolutionary algorithm. One batch ran with the same standard evolutionary algorithm, while the second batch ran with a version modified to seed input-source structures in the initial gates. These two batches were categorized and analyzed individually. The seeded batch performed noticeably better in categorization, providing evidence that seeding utilizing the structure from Chapter 4 is beneficial. The runs that passed categorization were simulated for power analysis, and the results were compared with a CMOS NAND gate. The results were better than the high-voltage subthreshold gate but still less power-efficient than the CMOS NAND gate. Possible explanations for this are discussed and future enhancements and research directions are presented in Chapter 7.

Audience: Graduate  Faculty 

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