Event
Ph.D. Research Proposal Exam: Daniel Zakzewski
Wednesday, October 30, 2024
12:00 p.m.
A.V.W. Room 1146
Maria Hoo
301 405 3681
mch@umd.edu
ANNOUNCEMENT: Ph.D. Research Proposal Exam
Name: Daniel Zakzewski
Committee:
Professor Alireza Khaligh (Chair)
Professor Xin Zan
Professor Sahil Shah
Date/time: October 30th, 2024 from 12:00PM to 2:00PM
Location: A.V.W. Room 1146
Title: Hybrid Neutral Point Clamped Circuits: Topology Analysis & Improvements
Abstract:
In high-powered electrical systems such as transportation electrification, renewable energy integration, and grid modernization; efficiency, size, and cost are crucial performance metrics.
Improvements in these areas facilitate further adoption of green technologies over combustion-based alternatives. The electronic power converter is central to these electrical systems, thus the research and optimization of power electronics circuits is essential for overall technology advancement. For applications exceeding 1000 volts, multilevel converters are the preferred choice because of their ability to generate high-quality output voltage, to decrease switching device voltage stresses, to increase efficiency, and to improve electromagnetic compatibility. However, of the available multilevel converter circuits, only a select few are used in contemporary systems.
This dissertation focuses on the hybrid neutral point clamped (Hybrid NPC) converter, a less commonly used class of power electronic circuits. This topology integrates features from the well-established neutral point clamped converter, flying capacitor converter, and cascaded H-bridge. Through comprehensive analysis, simulations, and experimentation, the hybrid NPC is shown to outperform the traditional alternative designs across the key performance metrics, thus establishing hybrid NPC as a viable solution for future high-powered electrical systems. Additionally, several innovations to the hybrid NPC topology are proposed which further improve the topology's efficiency, size, and cost. One innovation allows the use of lower voltage devices, which results in lower converter cost and size while increasing output waveform quality and efficiency. In another innovation, the output voltage of the converter is increased to achieve a higher power rating with minimal design modification. These innovations further the viability of hybrid ANPC.
The findings of this work provide valuable insights for future designers to adequately consider the adoption of the hybrid NPC topology, providing design guidance on device selection and control architecture to ease its implementation.
