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Stripped functionality logic locking (SFLL) is one of the leading logic locking methods in the current literature. While SFLL and its variations have good mathematical guarantees against resilience to various attacks, at its core SFLL is a circuit level technique and hence a naive implementation does not depend on system level details. Additionally, implementations of SFLL can come with high overhead, in particular the restore units needed to fully implement SFLL. We show that extending SFLL beyond circuit level boundaries and into the system design level through resource sharing and reuse significantly reduces SFLL implementation overhead. In particular, we examine two system design approaches that enable sharing at the system level to lower overall locking implementation overhead, as well as a clock gating method that relies on strategic application of SFLL at the datapath architecture level in order to reduce total system power.

3D ICs present a new dimension in the design and packaging of ICs and promise increased density, shorter wirelength, and improved performance. However, the complex interplay between placement and PPA increases substantially, particularly in regards to inter-tier TSVs needed for inter-tier connectivity, complicating the design process. In this dissertation, we describe three co-design approaches to 3D global placement and datapath architecture synthesis via HLS for timing, dynamic power, and TSV area optimization. We show that leveraging the greater flexibility afforded by the system-level perspective of HLS in the loop with feedback from global placement along with providing global placement with design details from HLS significantly enhances overall design quality. Our results show that our co-design approaches significantly reduces total negative slack (TNS), dynamic power consumption, and total TSV usage over conventional methods.