Event

ANNOUNCEMENT: Ph.D. Dissertation Defense

 

Name: Isaac McDaniel

 

Committee:

Prof. Ankur Srivastava (Chair)

Prof. Dana Dachman-Soled

Prof. Manoj Franklin

Prof. Shuvra Bhattacharyya

Prof. Ramani Duraiswami (Dean's Representative)

 

Date/Time: Tuesday, May 6, 2025 at 4:00pm-5:30pm

 

Location: AVW 2460

 

Title: IC Design for Age-Related Timing Degradation Using Machine Learning

 

Abstract:

Timing constraints are a major factor in modern IC design. In each clock cycle, data signals must leave one register, travel through the combinational logic of the design, and arrive at another register within a narrow window to satisfy both setup and hold time constraints. Therefore, static timing analysis (STA) is a major step in the design process. Designs often have very little margin in their timing, and many design revisions may be needed to ensure all paths' delays are within acceptable ranges. However, traditional STA considers the timing only of freshly manufactured circuits. As circuits age, effects such as negative bias temperature instability (NBTI) and hot carrier injection alter the timing properties of the device. For devices with a long expected service time, it may not be possible to neglect these effects when considering device timing constraints. In the dissertation, we investigate the design-level ramifications of NBTI and use machine learning (ML) to predict the end-of-life timing information for the design. We then explore design techniques that use this model to improve resilience against timing degradation.

 

We begin our work by evaluating the degree of NBTI degradation in path delays over the lifetime of an integrated circuit (IC). To remove some pessimism from timing constraints and increase the delay budget available to designers, we propose a machine learning technique to predict the effects of NBTI in a design. The remainder of the dissertation is devoted to exploring applications of our machine learning technique. Planned obsolescence refers to techniques used by companies to cause their previously sold products to perform poorly, usually intended to encourage the purchase of new products. We describe an approach to planned obsolescence which would allow companies to introduce performance penalties without tampering with the devices after delivering them to customers. Inserting delay buffers into the netlist at design time shortens the lifespan of the device as natural age-related degradation causes errors at a scheduled time. Global placement is a step in the IC design process which allocates standard cells and large macros across the chip canvas. We utilize our machine learning NBTI model to create an NBTI-aware design mode in a placement tool.