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ENEE408C Capstone Design Project: Modern Digital System Design

Course Description
A real-world digital system design experience that prepares students for careers in FPGA and ASIC design. Student teams use the Verilog hardware description language together with industry-standard simulation and synthesis tools to design medium-complexity digital chips that are ultimately configured and tested on FPGAs with real-world applications. Results from these projects will be presented through in-class presentations and written reports.

Prerequisite(s): ENEE 350

Corequisite(s): ENEE 446 (Recommended)

Course Objectives:

  • Understand HDL-based design using Verilog and FPGAs
  • Apply computer-aided design tools to design, implement, and debug hardware designs
  • Analyze design decisions to strike a cost-benefit balance in complex projects
  • Utilize teamwork and communication skills to schedule and execute a project schedule and hardware application design with other team members
  • Improve presentation and technical writing skills through oral presentations and written reports
  • Understand the short and long-term ethical implications of engineering decisions

Topics Covered:

  • Verilog syntax and structure
  • Verilog parameterization and module generation
  • Hardware design flow
  • Combinational logic design
  • Sequential logic design
  • Pipelining of modules
  • Hardware area minimization techniques
  • Clock speed maximization techniques
  • Communication protocols
  • FPGA implementation of real-world applications