Event
Ph.D. Research Proposal Exam: Isaac McDaniel
Thursday, August 1, 2024
1:00 p.m.
AV Williams 2328
Maria Hoo
301 405 3681
mch@umd.edu
ANNOUNCEMENT: Ph.D. Research Proposal Exam
Name: Isaac McDaniel
Committee:
Professor Ankur Srivastava (Chair)
Professor Dana Dachman-Soled
Professor Manoj Franklin
Date/time: Thursday, August 1, 2024 at 1:00 pm
Location: AV Williams 2328
Title: Logic Techniques for Security and Reliability in IC Design
Abstract:
In this dissertation proposal, we study logic optimization techniques to enhance reliability and security in IC designs. We review a previously secure logic obfuscation method and investigate how an attacker can extract a functionally correct circuit netlist from the obfuscated netlist. We then examine how machine learning-based aging models can enable IC designers to evaluate the reliability of their designs under negative-bias temperature instability in various use cases, when repeated physical simulation would be costly.
Logic obfuscation is a prominent approach to protect intellectual property within integrated circuits during fabrication. Some obfuscation techniques, including Full-Lock and InterLock, resist SAT attacks by inserting SAT-hard instances into the design, making Boolean satisfiability (SAT) attacks infeasible. We observe that this class of obfuscation leaves most of the original design topology visible to an attacker, who can reverse-engineer the original design given the functionality of the SAT-hard instance. We develop a novel attack which allows a SAT-capable attacker to efficiently learn this functionality, thereby unlocking designs obfuscated with Full-Lock which were previously thought secure. We empirically demonstrate the potency of our novel sensitization attack against benchmark circuits obfuscated with Full-Lock.
Negative-bias temperature instability (NBTI) is a primary age-related failure mechanism in current transistor technologies. NBTI is difficult to predict because it is input dependent, and simulating the design for a large variety of potential use cases becomes infeasible. As a result, most countermeasures either depend on data from manufactured ICs or monitor circuits during operation. However, we introduce a machine learning-based technique to predict NBTI degradation along timing paths in the design, parameterized for the chip's primary input distribution. This allows designers to anticipate aging effects for any use case without repeating detailed physical simulations. Our design-time NBTI predictions enable aging-aware CAD algorithms and manual design to mitigate NBTI during the revision process.
